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| HM624256A Series 262144-word x 4-bit High Speed CMOS Static RAM The Hitachi HM624256A is a high speed 1M Static RAM organized as 262,144-word x 4-bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high speed circuit designing technology. It is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit MPU. The HM624256A, packaged in a 400-mil plastic SOJ is available for high density mounting. Pin Arrangement A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O 1 I/O 2 I/O 3 I/O 4 WE Features * Single 5 V supply and high density 28-pin package (DIP and SOJ) * High speed Access time: 20/25/35 ns (maximum) * Low power dissipation Active mode: 350 mW (typical) Standby mode: 100 W (typical) * Completely static memory No clock or timing strobe required * Equal access and cycle time * Directly TTL compatible All inputs and outputs A10 CS OE VSS Pin Description Pin name Function --------------------------------------------- A0 - A17 Address --------------------------------------------- I/O1 - I/O4 Input/output --------------------------------------------- CS Chip select --------------------------------------------- OE Output enable --------------------------------------------- WE Write enable --------------------------------------------- VCC Power supply --------------------------------------------- VSS Ground --------------------------------------------- Ordering Information Type No. Access time Package --------------------------------------------- HM624256AP-20 20 ns 400 mil HM624256AP-25 25 ns 28-pin HM624256AP-35 35 ns plastic DIP -------------------------------- (DP-28C) HM624256ALP-20 20 ns HM624256ALP-25 25 ns HM624256ALP-35 35 ns --------------------------------------------- HM624256AJP-20 20 ns 400 mil HM624256AJP-25 25 ns 28-pin HM624256AJP-35 35 ns plastic SOJ -------------------------------- (CP-28D) HM624256ALJP-20 20 ns HM624256ALJP-25 25 ns HM624256ALJP-35 35 ns --------------------------------------------- 1 HM624256A Series Block Diagram A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 I/O2 I/O3 I/O4 Input data control Column I/O Column decoder HM624256A Series Row decoder Memory array 512 x 2048 VCC VSS A0 A1 A11A12A13A14A15A16A17 CS WE OE Function Table CS OE WE Mode VCC current I/O pin Ref. cycle ----------------------------------------------------------------------------------------------- H X X Not selected ISB, ISB1 High-Z -- ----------------------------------------------------------------------------------------------- L L H Read ICC Dout Read cycle (1) - (3) ----------------------------------------------------------------------------------------------- L H L Write ICC Din Write cycle (1) ----------------------------------------------------------------------------------------------- L L L Write ICC Din Write cycle (2) ----------------------------------------------------------------------------------------------- Note: X: H or L Absolute Maximum Ratings Parameter Symbol Value Unit ----------------------------------------------------------------------------------------------- Voltage on any pin relative to VSS Vin -0.5*1 to +7.0 V ----------------------------------------------------------------------------------------------- Power dissipation PT 1.0 W ----------------------------------------------------------------------------------------------- Operating temperature range Topr 0 to +70 C ----------------------------------------------------------------------------------------------- Storage temperature range Tstg -55 to +125 C ----------------------------------------------------------------------------------------------- Storage temperature range under bias Tbias -10 to +85 C ----------------------------------------------------------------------------------------------- Note: 1. Vin min = -2.0 V for pulse width 10 ns 2 HM624256A Series Recommended DC Operating Conditions (Ta = 0 to +70C) HM624256A Series Parameter Symbol Min Typ Max Unit ----------------------------------------------------------------------------------------------- Supply voltage VCC 4.5 5.0 5.5 V --------------------------------------------------------------- VSS 0 0 0 V ----------------------------------------------------------------------------------------------- Input high (logic 1) voltage VIH 2.2 -- 6.0 V ----------------------------------------------------------------------------------------------- Input low (logic 0) voltage VIL -0.5*1 -- 0.8 V ----------------------------------------------------------------------------------------------- Note: 1. VIL min = -2.0 V for pulse width 10 ns DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM624256A-20 HM624256A-25/35 ------------------ ------------------ Parameter Symbol Min Typ*1 Max Min Typ*1 Max Unit Test conditions ----------------------------------------------------------------------------------------------- Input leakage |ILI| -- -- 2.0 -- -- 2.0 A VCC = max current Vin = VSS to VCC ----------------------------------------------------------------------------------------------- Output leakage |ILO| -- -- 2.0 -- -- 2.0 A CS = VIH current VI/O = VSS to VCC ----------------------------------------------------------------------------------------------- Operating power ICC -- -- 150 -- -- 120 mA CS = VIL, supply current II/O = 0 mA, min cycle ----------------------------------------------------------------------------------------------- Standby power ISB -- -- 60 -- -- 40 mA CS = VIH, supply current min cycle ----------------------------------------------------------------------------------------------- Standby power ISB1 -- 0.02 2.0 -- 0.02 2.0 mA CS VCC - 0.2 V supply current (1) --------------------------------------------------------- 0 V Vin 0.2 V or ISB1*2 -- -- 100*2 -- -- 100*2 A Vin VCC - 0.2 V ----------------------------------------------------------------------------------------------- Output low voltage VOL -- -- 0.4 -- -- 0.4 V IOL = 8 mA ----------------------------------------------------------------------------------------------- Output high voltage VOH 2.4 -- -- 2.4 -- -- V IOH = -4 mA ----------------------------------------------------------------------------------------------- Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. LP and LJP version Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Max Unit Test conditions ----------------------------------------------------------------------------------------------- pF Vin = 0 V Input capacitance Cin -- 5*2 -------- 6*3 ----------------------------------------------------------------------------------------------- -- 8 pF VI/O = 0 V Input/output capacitance CI/O ----------------------------------------------------------------------------------------------- Note: 1. This parameter is sampled and not 100% tested. 2. SOJ package 3. DIP package 3 HM624256A Series Test Conditions * Input pulse levels: 0V to 3.0 V * Input rise and fall times: 4 ns * Input timing reference levels: 1.5 V +5V 480 Dout 255 30 pF *1 Dout 255 HM624256A Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) * Output timing reference levels: 1.5 V * Output load: See figures +5V 480 5 pF *1 Output load (A) Output load (B) (For tCHZ, tOHZ, tCLZ, tOLZ, tWHZ and tOW) Note: 1. Including scope and jig Read Cycle HM624256A-20 HM624256A-25 HM624256A-35 -------------- -------------- -------------- Parameter Symbol Min Max Min Max Min Max Unit ----------------------------------------------------------------------------------------------- Read cycle time tRC 20 -- 25 -- 35 -- ns ----------------------------------------------------------------------------------------------- Address access time tAA -- 20 -- 25 -- 35 ns ----------------------------------------------------------------------------------------------- Chip select access time tACS -- 20 -- 25 -- 35 ns ----------------------------------------------------------------------------------------------- Chip selection to output in low-Z tCLZ*1 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Output enable to output valid tOE -- 10 -- 12 -- 15 ns ----------------------------------------------------------------------------------------------- Output enable to output in low-Z tOLZ*1 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Chip deselection to output in high-Z tCHZ*1 0 10 0 12 0 15 ns ----------------------------------------------------------------------------------------------- Chip disable to output in high-Z tOHZ*1 0 10 0 10 0 10 ns ----------------------------------------------------------------------------------------------- Output hold from address change tOH 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Chip selection to power up time tPU 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Chip deselection to power tPD -- 12 -- 15 -- 25 ns down time ----------------------------------------------------------------------------------------------- 4 HM624256A Series Read Timing Waveform (1) *1, *2 HM624256A Series t RC Address t AA OE t OE t OLZ t ACS t CLZ Dout t OHZ t CHZ Valid Data t OH CS Read Timing Waveform (2) *2, *3, *5 t RC Address t AA t OH Dout Valid Data t OH 5 HM624256A Series Read Timing Waveform (3) *1, *2, *4, *5 HM624256A Series CS t ACS t CLZ Dout High Impedance t PU VCC supply I CC current I SB 50 % Valid Data t PD High Impedance 50 % t CHZ Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 2. WE is high for read cycle. 3. Device is continuously selected, CS = VIL. 4. Address valid prior to or coincident with CS transition low. 5. OE = VIL Write Cycle HM624256A-20 HM624256A-25 HM624256A-35 -------------- -------------- -------------- Parameter Symbol Min Max Min Max Min Max Unit ----------------------------------------------------------------------------------------------- Write cycle time tWC 20 -- 25 -- 35 -- ns ----------------------------------------------------------------------------------------------- Chip selection to end of write tCW 15 -- 17 -- 25 -- ns ----------------------------------------------------------------------------------------------- Address valid to end of write tAW 16 -- 20 -- 30 -- ns ----------------------------------------------------------------------------------------------- Address setup time tAS 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write pulse width tWP 15 -- 17 -- 25 -- ns ----------------------------------------------------------------------------------------------- Write recovery time tWR 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Output disable to output in high-Z tOHZ*1 0 10 0 10 0 10 ns ----------------------------------------------------------------------------------------------- Write to output in high-Z tWHZ*1 0 12 0 15 0 15 ns ----------------------------------------------------------------------------------------------- Data to write time overlap tDW 12 -- 15 -- 20 -- ns ----------------------------------------------------------------------------------------------- Data hold from write time tDH 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Output active from end of write tOW*1 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 6 HM624256A Series Write Timing Waveform (1) HM624256A Series t WC Address t WR*3 OE t CW CS t AS WE t OHZ *4 Dout t WP *2 t DW Valid Data t DH *5 t AW Din 7 HM624256A Series Write Timing Waveform (2) *6 HM624256A Series t WC Address t CW CS *5 t WR *3 t WP*2 WE t AS t OH t WHZ *4 *7 *8 t OW Dout t DW Din t DH *9 Valid Data Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap (tWP) of a low CS and a low WE. 3. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low. (OE = VIL) 7. Dout is the same phase of write data of this write cycle. 8. Dout is the read data of next address. 9. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 8 HM624256A Series Low VCC Date Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. HM624256A Series Parameter Symbol Min Typ Max Unit Test conditions ----------------------------------------------------------------------------------------------- VCC for data retention VDR 2.0 -- -- V CS VCC - 0.2 V, ------------------------------------------------------------------------ Vin VCC - 0.2 V or Data retention current ICCDR -- 2 50*1 A 0 V Vin 0.2 V ------------------------------------------------------------------------ Chip deselect to data retention time tCDR 0 -- -- ns ------------------------------------------------------------------------ Operation recovery time tR 5 -- -- ms ----------------------------------------------------------------------------------------------- Note: 1. VCC = 3.0 V Low VCC Data Retention Timing Waveform Data retention mode V CC 4.5 V t CDR 2.2 V V DR CS 0V CS VCC - 0.2 V tR 9 |
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